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1/33 september 2004 STM690A, stm692a, stm703 stm704, stm802, stm805, stm817/8/9 5v supervisor with battery switchover * contact local st sales office for availability. features summary 5v operating voltage nvram supervisor for external lpsram chip-enable gating (stm818 only) for external lpsram (7ns max prop delay) rst and rst outputs 200ms (typ) t rec watchdog timer - 1.6sec (typ) automatic battery switchover low battery supply current - 0.4a (typ) power-fail comparator (pfi/pfo ) low supply current - 40a (typ) guaranteed rst (rst) assertion down to v cc = 1.0v operating temperature: ?40c to 85c (industrial grade) figure 1. packages table 1. device options note: 1. all rst and rst outputs are push-pull. 8 1 so8 (m) tssop8 3x3 (ds)* watchdog input active- low rst (1) active- high rst (1) manual reset input battery switch- over power-fail comparator chip- enable gating battery freshness seal STM690A ?? ? ? stm692a ?? ? ? stm703 ???? stm704 ???? stm802l/m ?? ? ? stm805l ???? stm817l/m ?? ? ? ? stm818l/m ?? ? ? ? stm819l/m ???? ?
STM690A/692a/703/ 704/802/805/817/818/819 2/33 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram (STM690A/692a/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram (stm703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. logic diagram (stm818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5. STM690A/692a/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. stm703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 7. stm818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 8. block diagram (STM690A/692a/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 9. block diagram (stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 10.block diagram (stm818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 11.hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 push-button reset input (stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 watchdog input (not available on stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 back-up battery switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. i/o status in battery back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip-enable gating (stm818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 chip enable input (stm818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 chip enable output (stm818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 12.chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13.chip enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 power-fail input/output (not available on stm818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14.power-fail comparator waveform (stm817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15.power-fail comparator waveform (STM690A/692a/703/704/802/805) . . . . . . . . . . . . . 13 using a supercap? as a backup power source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 negative-going v cc transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 battery freshness seal (stm817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16.using a supercap? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17.freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 18.v bat -to-v out on-resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 19.supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 20.v pfi threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 21.reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 22.power-up t rec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 23.normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 24.watchdog time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 25.e to e con on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 26.pfi to pfo propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 27.rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 28.rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29.rst response time (assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 30.rst response time (assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 31.power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 32.power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 33.v cc to reset propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 34.maximum transient duration vs. reset threshold overdrive. . . . . . . . . . . . . . . . . . . . . 22 figure 35.e to e con propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 36.e to e con propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 37.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 38.mr timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 39.watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 40.so8 ? 8-lead plastic small outline, 150 mils body width, package mech. drawing. . . . 28 table 8. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . 28 figure 41.tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, outline . . . . . . . . . . . 29 table 9. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, mechanical data . . . . 29 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 11. marking description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM690A/692a/703/ 704/802/805/817/818/819 4/33 summary description the STM690A/692a/703/704/802/805/817/818/ 819 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect exter- nal lpsram. a precision voltage reference and comparator monitors the v cc input for an out-of- tolerance condition. when an invalid v cc condi- tion occurs, the reset output (rst ) is forced low (or high in the case of rst). these devices also offer a watchdog timer (except for stm703/704/ 819) as well as a power-fail comparator (except for stm818) to provide the system with an early warning of impending power failure. these devices are available in a standard 8-pin soic package or a space-saving 8-pin tssop package. figure 2. logic diagram (STM690A/692a/802/ 805/817) note: 1. for stm805, reset output is active-high. figure 3. logic diagram (stm703/704/819) figure 4. logic diagram (stm818) table 2. signal names note: 1. stm818 ai07894 v cc v bat STM690A/ 692a/802/ 805/817 v ss v out rst(rst) (1) wdi pfi pfo ai07895 v cc v bat stm703/ 704/819 v ss v out rst mr pfi pfo mr push-button reset input wdi watchdog input rst active-low reset output rst active-high reset output e (1) chip enable input e con (1) conditioned chip enable output v out supply voltage output v cc supply voltage v bat back-up supply voltage pfi power-fail input pfo power-fail output v ss ground ai07896 v cc v bat stm818 v ss v out rst wdi e e con
5/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 5. STM690A/692a/802/805/817 connections note: 1. for stm805, reset output is active-high. figure 6. stm703/704/819 connections figure 7. stm818 connections 1 pfo pfi wdi rst(rst) (1) v cc v out v bat v ss ai07889 so8/tssop8 2 3 4 8 7 6 5 1 pfo pfi mr rst v cc v out v bat v ss ai07890 so8/tssop8 2 3 4 8 7 6 5 1 e con e wdi rst v cc v out v bat v ss ai07892 so8/tssop8 2 3 4 8 7 6 5
STM690A/692a/703/ 704/802/805/817/818/819 6/33 pin descriptions mr . a logic low on /mr asserts the reset output. reset remains asserted as long as mr is low and for t rec after mr returns high. this active-low input has an internal pull-up. it can be driven from a ttl or cmos logic line, or shorted to ground with a switch. leave open if unused. wdi. if wdi remains high or low for 1.6sec, the in- ternal watchdog timer runs out and reset is trig- gered. the internal watchdog timer clears while reset is asserted or when wdi sees a rising or fall- ing edge. the watchdog function can be disabled by allow- ing the wdi pin to float. rst . pulses low for t rec when triggered, and stays low whenever v cc is below the reset threshold or when mr is a logic low. it remains low for t rec after either v cc rises above the reset threshold, the watchdog triggers a reset, or mr goes from low to high. rst. pulses high for t rec when triggered, and stays high whenever v cc is above the reset threshold or when mr is a logic high. it remains high for t rec after either v cc falls below the reset threshold, the watchdog triggers a reset, or mr goes from high to low. v out . when v cc is above the switchover voltage (v so ), v out is connected to v cc through a p- channel mosfet switch. when v cc falls below v so , v bat connects to v out . connect to v cc if no battery is used. v bat . when v cc falls below v so , v out switches from v cc to v bat . when v cc rises above v so + hysteresis, v out reconnects to v cc . v bat may ex- ceed v cc . connect to v cc if no battery is used. e . the input to the chip-enable gating circuit. con- nect to ground if unused. e con . e con goes low only when e is low and re- set is not asserted. if e con is low when reset is as- serted, e con will remain low for 15s or until e goes high, whichever occurs first. in the disabled mode, e con is pulled up to v out . pfi. when pfi is less than v pfi or when v cc falls below 2.4v (or v so ), pfo goes low; otherwise, pfo remains high. connect to ground if unused. pfo . when pfi is less than v pfi , or v cc falls be- low 2.4v (or v so ), pfo goes low; otherwise, pfo remains high. leave open if unused. table 3. pin description pin name function stm818 STM690A stm692a stm802 stm817 stm703 stm704 stm819 stm805 ??6?mr push-button reset input 66?6wdiwatch dog input 777?rst active-low reset output ???7rstactive-high reset output 1111 v out supply output for external lpsram 2222 v cc supply voltage 8888 v bat backup-battery input 4???e chip enable input 5??? e con conditioned chip enable output ?444pfipfi power-fail input ?555pfo pfo power-fail output 3333 v ss ground
7/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 8. block diagram (STM690A/692a/802/805/817) note: 1. for stm805, reset output is active-high. figure 9. block diagram (stm703/704/819) ai07897 watchdog timer v rst v out compare compare compare t rec generator v pfi v bat v so v cc pfi wdi rst(rst) (1) pfo ai07898 v rst v out compare compare compare t rec generator v pfi v bat v so v cc pfi mr rst pfo
STM690A/692a/703/ 704/802/805/817/818/819 8/33 figure 10. block diagram (stm818) figure 11. hardware hookup note: 1. for STM690A/692a/802/805/817/818. 2. for stm818 only. 3. not available on stm818. 4. for stm703/704/819. ai07899a watchdog timer v rst v out e con compare compare t rec generator e con output control v bat v so v cc wdi rst e e v cc ai07893 v cc e con (2) mr (4) v out e v cc lpsram pfi (3) 0.1 f 0.1 f STM690A/692a/ 703/704/802/805/ 817/818/819 wdi (1) pfo (3) rst to microprocessor reset unregulated voltage regulator v cc v in r1 r2 push-button from microprocessor e (2) v bat to microprocessor nmi
9/33 STM690A/692a/703/ 704/802/805/817/818/819 operation reset output the STM690A/692a/703/704/802/805/817/818/ 819 supervisor asserts a reset signal to the mcu whenever v cc goes below the reset threshold (v rst ), a watchdog time-out occurs, or when the push-button reset input (mr ) is taken low. rst is guaranteed to be a logic low (logic high for stm805) for 0v < v cc < v rst if v bat is greater than 1v. without a back-up battery, rst is guar- anteed valid down to v cc =1v. during power-up, once v cc exceeds the reset threshold an internal timer keeps rst low for the reset time-out period, t rec . after this interval rst returns high. if v cc drops below the reset threshold, rst goes low. each time rst is asserted, it stays low for at least the reset time-out period (t rec ). any time v cc goes below the reset threshold the internal timer clears. the reset timer starts when v cc returns above the reset threshold. push-button reset input (stm703/704/819) a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rec (see figure 38., page 24 ) after it returns high. the mr input has an internal 40k ? pull-up resistor, allowing it to be left open if not used. this input can be driven with ttl/cmos-logic levels or with open-drain/ collector outputs. connect a normally open mo- mentary switch from mr to gnd to create a man- ual reset function; external debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environment, connect a 0.1f capacitor from mr to gnd to provide ad- ditional noise immunity. mr may float, or be tied to v cc when not used. watchdog input (not available on stm703/ 704/819) the watchdog timer can be used to detect an out- of-control mcu. if the mcu does not toggle the watchdog input (wdi) within t wd (1.6sec typ), the reset is asserted. the internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling wdi (high-to-low or low-to-high), which can detect pulses as short as 50ns. if wdi is tied high or low, a reset pulse is triggered every 1.8sec (t wd + t rec ). the timer remains cleared and does not count for as long as reset is asserted. as soon as reset is re- leased, the timer starts counting (see figure 39., page 24 ). note: the watchdog function may be disabled by floating wdi or tri-stating the driver connected to wdi. when tri-stated or disconnected, the maxi- mum allowable leakage current is 10ua and the maximum allowable load capacitance is 200pf. note: input frequency greater than 20ns (50mhz) will be filtered.
STM690A/692a/703/ 704/802/805/817/818/819 10/33 back-up battery switchover in the event of a power failure, it may be necessary to preserve the contents of external sram through v out . with a backup battery installed with voltage v bat , the devices automatically switch the sram to the back-up supply when v cc falls. note: if back-up battery is not used, connect both v bat and v out to v cc . this family of supervisors does not always con- nect v bat to v out when v bat is greater than v cc . v bat connects to v out (through a 100 ? switch) when v cc is below v rst and v bat . this is done to allow the back-up battery (e.g., a 3.6v lithium cell) to have a higher voltage than v cc . assuming v bat > 2.0v, switchover at v so ensures that battery back-up mode is entered before v out gets too close to the 2.0v minimum required to re- liably retain data in most external srams. when v cc recovers, hysteresis is used to avoid oscilla- tion around the v so point. v out is connected to v cc through a 3 ? pmos power switch. note: the back-up battery may be removed while v cc is valid, assuming v bat is adequately decou- pled (0.1f typ), without danger of triggering a re- set. table 4. i/o status in battery back-up chip-enable gating (stm818 only) internal gating of the chip enable (e ) signal pre- vents erroneous data from corrupting the external cmos ram in the event of an undervoltage con- dition. the stm818 uses a series transmission gate from e to e con (see figure 12., page 11 ). during normal operation (reset not asserted), the e transmission gate is enabled and passes all e transitions. when reset is asserted, this path be- comes disabled, preventing erroneous data from corrupting the cmos ram. the short e propaga- tion delay from e to e con enables the stm818 to be used with most ps. if e is low when reset as- serts, e con remains low for typically 15s to per- mit the current write cycle to complete. connect e to v ss if unused. chip enable input (stm818 only) the chip-enable transmission gate is disabled and e is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the chip-enable transmission gate disables and e immediately be- comes high impedance if the voltage at e is high. if e is low when reset asserts, the chip-enable transmission gate will disable 15s after reset as- serts (see figure 13., page 11 ). this permits the current write cycle to complete during power- down. any time a reset is generated, the chip-enable transmission gate remains disabled and e remains high impedance (regardless of e activity) for the reset time-out period. when the chip enable trans- mission gate is enabled, the impedance of e ap- pears as a 40 ? resistor in series with the load at e con . the propagation delay through the chip-en- able transmission gate depends on v cc , the source impedance of the drive connected to e , and the loading on e con . the chip enable propa- gation delay is production tested from the 50% point on e to the 50% point on e con using a 50 ? driver and a 50pf load capacitance (see figure 37., page 24 ). for minimum propagation delay, minimize the capacitive load at e con and use a low-output impedance driver. chip enable output (stm818 only) when the chip-enable transmission gate is en- abled, the impedance of e con is equivalent to a 40 ? resistor in series with the source driving e . in the disabled mode, the transmission gate is off and an active pull-up connects e con to v out (see figure 12., page 11 ). this pull-up turns off when the transmission gate is enabled. pin status v out connected to v bat through internal switch v cc disconnected from v out pfi disabled pfo logic low e high impedance e con logic high wdi watchdog timer is disabled wdo logic low mr disabled rst logic low rst logic high v bat connected to v out
11/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 12. chip-enable gating figure 13. chip enable waveform ai08802 v rst v out v cc compare e con t rec generator e con output control rst e ai08803b rst e v cc v rst v bat e con trec trec 15s
STM690A/692a/703/ 704/802/805/817/818/819 12/33 power-fail input/output (not available on stm818) the power-fail input (pfi) is compared to an inter- nal reference voltage (independent from the v rst comparator). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo ) will go low. this function is intended for use as an un- dervoltage detector to signal a failing power sup- ply. typically pfi is connected through an external voltage divider (see figure 11., page 8 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the STM690A/692a/703/ 704/802/805/817/818/819 supervisor or the mi- croprocessor drops below the minimum operating voltage. during battery back-up, the power-fail comparator turns off and pfo goes (or remains) low (see fig- ure 14 and figure 15., page 13 ). this occurs after v cc drops below 2.4v (or v so ). when power re- turns, pfo is forced high (stm817/819 only), irre- spective of v pfi for the write protect time (t rec ). at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. pfo may be connected to mr on the stm703/704/818 so that a low voltage on pfi will generate a reset output. applications information these supervisor circuits are not short-circuit pro- tected. shorting v out to ground - excluding pow- er-up transients such as charging a decoupling capacitor - destroys the device. decouple both v cc and v bat pins to ground by placing 0.1f ca- pacitors as close to the device as possible. figure 14. power-fail comparator waveform (stm817/818/819) ai08804a v cc v rst v so (or 2.4v) trec rst to e con delay (stm818) rst e con (stm818) pfo (stm817/819) pfo follows pfi pfo follows pfi
13/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 15. power-fail comparator waveform (STM690A/692a/703/704/802/805) ai08832a v cc v rst 2.4v (or v so ) trec rst pfo pfo follows pfi pfo follows pfi
STM690A/692a/703/ 704/802/805/817/818/819 14/33 using a supercap? as a backup power source supercaps? are capacitors with extremely high capacitance values (e.g., order of 0.47f) for their size. figure 16 shows how to use a supercap as a back-up power source. the supercap may be connected through a diode to the 5v input. since v bat can exceed v cc while v cc is above the reset threshold, there are no special precautions when using these supervisors with a supercap. negative-going v cc transients the STM690A/692a/703/704/802/805/817/818/ 819 supervisor are relatively immune to negative- going v cc transients (glitches). figure 34., page 22 shows typical transient duration ver- sus reset comparator overdrive (for which the STM690A/692a/703/704/802/805/817/818/819 will not generate a reset pulse). the graph was generated using a negative pulse applied to v cc , starting at v rst + 0.3v and ending below the reset threshold by the magnitude indicated (comparator overdrive). the graph indicates the maximum pulse width a negative v cc transient can have without causing a reset pulse. as the magnitude of the transient increases (further below the thresh- old), the maximum allowable pulse width decreas- es. any combination of duration and overdrive which lies under the curve will not generate a re- set signal. typically, a v cc transient that goes 100mv below the reset threshold and lasts 40s or less will not cause a reset pulse. a 0.1f bypass capacitor mounted as close as possible to the v cc pin provides additional transient immunity. battery freshness seal (stm817/818/819) the battery freshness seal disconnects the back- up battery from internal circuitry and v out until it is needed. this allows an oem to ensure that the back-up battery connected to v bat will be fresh when the final product is put to use. to enable the freshness seal: 1. connect a battery to v bat ; 2. ground pfo ; 3. bring v cc above the reset threshold and hold it there until reset is deasserted following the reset timeout period; and 4. bring v cc down again (figure 17 ). use the same procedure for the stm818, but ground e con instead of pfo . once the battery freshness seal is enabled (disconnecting the back-up battery from internal circuitry and any- thing connected to v out ), it remains enabled until v cc is brought above v rst . figure 16. using a supercap? figure 17. freshness seal enable waveform ai08805 stmxxx v bat v cc v out 5v gnd rst to external sram to p ai08806 rst pfo (stm817/819) v cc v rst e con (stm818) trec (externally held at 0v) (externally held at 0v) e con out state latched at 1/2 t rec , freshness seal enabled pfo out state latched at 1/2 t rec , freshness seal enabled
15/33 STM690A/692a/703/ 704/802/805/817/818/819 typical operating characteristics note: typical values are at t a = 25c figure 18. v bat -to-v out on-resistance vs. temperature figure 19. supply current vs. temperature (no load) 100 120 140 160 180 200 220 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] v bat - to - v out on-resistance [ ? ] v bat = 2v v bat = 3v v bat = 3.3v v bat = 5v v cc = 0v ai09140 0 5 10 15 20 25 30 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 temperature [ c] supply current [a] 2.5v 3.3v 3.6v 5.0v 5.5v ai09141
STM690A/692a/703/ 704/802/805/817/818/819 16/33 figure 20. v pfi threshold vs. temperature figure 21. reset comparator propagation delay vs. temperature figure 22. power-up t rec vs. temperature 1.225 1.230 1.235 1.240 1.245 1.250 1.255 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature [ c] v pfi threshold [v] v cc = 2.5v v cc = 3.3v v cc = 5v v bat = 3.0v ai09142 10 12 14 16 18 20 22 24 ?60 ?40 ?20 0 20 40 60 80 100 temperature [ c] propagation delay [s] v bat = 3.0v 100mv overdrive ai09143 ai09144 195 200 205 210 215 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature [ c] t rec [ms]
17/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 23. normalized reset threshold vs. temperature figure 24. watchdog time-out period vs. temperature figure 25. e to e con on-resistance vs. temperature 0.994 0.996 0.998 1.000 1.002 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] normalized reset threshold [v] v bat = 3.0v ai09145 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 1.72 1.74 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature [ c] watchdog time-out period [sec] ai09146 30 40 50 60 70 80 90 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] e to e con on-resistance [ ? ] v cc = 3v ai09147
STM690A/692a/703/ 704/802/805/817/818/819 18/33 figure 26. pfi to pfo propagation delay vs. temperature figure 27. r st output voltage vs. supply voltage 0 1 2 3 4 5 6 7 8 9 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] propagation delay [s] ai09148 0 1 2 3 4 5 6 rst output voltage [v] 500 ms/div v rst v cc ai09149
19/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 28. rst output voltage vs. supply voltage figure 29. r st response time (assertion) 0 1 2 3 4 5 6 rst output voltage [v] 500 ms/div v cc v rst ai09150 0 1 2 3 4 5 6 v cc level [v] v rst v cc ai09151 2 s/div
STM690A/692a/703/ 704/802/805/817/818/819 20/33 figure 30. rst response time (assertion) figure 31. power-fail comparator response time (assertion) 0 1 2 3 4 5 6 v cc level [v] 2s/div v rst v cc ai09152 0 1 2 3 4 5 6 v pfo level [v] 1.15 1.20 1.25 1.30 1.35 1.40 1.45 v pfi level [v] pfi pfo 2s/div ai09153
21/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 32. power-fail comparator response time (de-assertion) figure 33. v cc to reset propagation delay vs. temperature 0 1 2 3 4 5 6 v pfo level (v) 1.15 1.20 1.25 1.30 1.35 1.40 1.45 v pfi level (v) pfi pfo 2 s/div ai09154 0 10 20 30 40 50 60 ?60 ?40 ?20 0 20 40 60 80 100 temperature [ c] propagation delay [s] 10v/ms 1v/ms 0.25v/ms ai09155
STM690A/692a/703/ 704/802/805/817/818/819 22/33 figure 34. maximum transient duration vs. reset threshold overdrive figure 35. e to e con propagation delay vs. temperature 0 50 100 150 200 250 1 10 100 1000 10000 reset comparator overdrive, v rst ? v cc [mv] transient duration [s] ai09156 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] e to e con propagation delay [ns] e falling e rising ai09157
23/33 STM690A/692a/703/ 704/802/805/817/818/819 maximum rating stressing the device above the rating listed in the absolute maximum ratings? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 5. absolute maximum ratings note: 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 t o 150 seconds). dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 6 , operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 6. operating and ac measurement conditions symbol parameter value unit t stg storage temperature (v cc off) ?55 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc +0.3 v v cc /v bat supply voltage ?0.3 to 6.0 v i o output current 20 ma p d power dissipation 320 mw parameter STM690A/692a/703/704/802/ 805/817/818/819 unit v cc /v bat supply voltage 1.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing ref. voltages 0.3 to 0.7v cc v
STM690A/692a/703/ 704/802/805/817/818/819 24/33 figure 36. e to e con propagation delay test circuit note: 1. c l includes load capacitance and scope probe capacitance. figure 37. ac testing input/output waveforms figure 38. mr timing waveform note: 1. rst for stm805. figure 39. watchdog timing ai08854 v bat e con v cc v cc 3.6v 50pf c l (1) 25 ? equivalent source impedance 50 ? cable 50 ? 50 ? stmxxx gnd e ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc ai07837a rst (1) mr tmlrl trec tmlmh ai07891 rst wdi v cc trec twd
25/33 STM690A/692a/703/ 704/802/805/817/818/819 table 7. dc and ac characteristics sym alter- native description test condition (1) min typ max unit v cc , v bat (2) operating voltage t a = ?40 to +85c 1.2 (3) 5.5 v i cc v cc supply current excluding i out (v cc < 5.5v) 25 60 a v cc supply current in battery back-up mode excluding i out (v bat = 2.3v, v cc = 2.0v, mr = v cc ) 25 35 a i bat (4) v bat supply current in battery back-up mode excluding i out (v bat = 3.6v) 0.4 1.0 a v out1 v out voltage (active) i out1 = 5ma (5) v cc ? 0.03 v cc ? 0.015 v i out1 = 75ma v cc ? 0.3 v cc ? 0.15 v i out1 = 250a, v cc > 2.5v (5) v cc ? 0.0015 v cc ? 0.0006 v v out2 v out voltage (battery back-up) i out2 = 250a, v bat = 2.3v v bat ? 0.1 v bat ? 0.034 v i out2 = 1ma, v bat = 2.3v v bat ? 0.14 v v cc to v out on-resistance 34 ? v bat to v out on-resistance 100 ? i li input leakage current (mr ) 4.5v < v cc < 5.5v 75 125 300 a input leakage current (pfi) 0v = v in = v cc ?25 2 +25 na input leakage current (wdi) (6) wdi = v cc , time average 120 160 a wdi = gnd, time average ?20 ?15 a v ih input high voltage (mr ) 4.5v < v cc < 5.5v 2.0 v v ih input high voltage (wdi) v rst (max) < v cc < 5.5v 0.7v cc v v il input low voltage (mr ) 4.5v < v cc < 5.5v 0.8 v v il input low voltage (wdi) v rst (max) < v cc < 5.5v 0.3v cc v v ol output low voltage (pfo , rst , rst) v cc = v rst (max), i sink = 3.2ma 0.3 v output low voltage (e con ) v cc = v rst (max), i out = 1.6ma, e = 0v 0.2v cc v v ol output low voltage (rst ) i sink = 50a; v cc = 1.0v; v bat = v cc ; t a = 0c to 85c 0.3 v i sink = 100a; v cc = 1.2v; v bat = v cc 0.3 v
STM690A/692a/703/ 704/802/805/817/818/819 26/33 v oh output high voltage (rst , rst) i source = 1ma, v cc = v rst (max) 2.4 v output high voltage (e con ) v cc = v rst (max), i out = 1.6ma, e = v cc 0.8v cc v output high voltage (pfo ) i source = 75a, v cc = v rst (max) 0.8v cc v v oh output high voltage i source = 4a; v cc = 1.1v; v bat = v cc ; t a = 0c to 85c 0.8 v i source = 4a; v cc = 1.2v; v bat = v cc 0.9 v v ohb v oh battery back-up (e con , rst , rst) i source = 100a, 0.8v bat v power-fail comparator (not available on stm818) v pfi pfi input threshold pfi falling (v cc = 5v) all other versions 1.20 1.25 1.30 v stm802 1.225 1.250 1.275 v t pfd pfi to pfo propagation delay 2s i sc pfo output short to gnd current v cc = 5v, v pfo = 0v 0.10.752.0ma battery switchover v so battery back-up switchover voltage (7,8) (v cc < v bat & v cc < v rst ) power-down v rst > v bat v bat v v rst < v bat v rst v power-up v rst > v bat v bat v v rst < v bat v rst v hysteresis 40 mv reset thresholds v rst reset threshold (9) STM690A/703, stm8xxl 4.50 4.65 4.75 v stm692a/704, stm8xxm 4.25 4.40 4.50 v reset threshold hysteresis 25 mv v cc to rst delay (from v rst , v cc falling at 10v/ms) stm817/818/819 100 s t rec rst pulse width 140 200 280 ms sym alter- native description test condition (1) min typ max unit
27/33 STM690A/692a/703/ 704/802/805/817/818/819 note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.75v to 5.5v for ?l? versions; v cc = 4.5v to 5.5v for ?m? ver- sions; and v bat = 2.8v (except where noted). 2. v cc supply current, logic input leakage, watchdog functionality, push-button reset functionality, pfi functionality, state of rst and rst tested at v bat = 3.6v, and v cc = 5.5v. the state of rst or rst and pfo is tested at v cc = v cc (min). either v cc or v bat can go to 0v if the other is greater than 2.0v. 3. v cc (min) = 1.0v for t a = 0c to +85c. 4. tested at v bat = 3.6v, v cc = 3.5v and 0v. 5. guaranteed by design. 6. wdi input is designed to be driven by a three-state output device. to float wdi, the ?high impedance mode? of the output devi ce must have a maximum leakage current of 10a and a maximum output capacitance of 200pf. the output device must also be able to source and sink at least 200a when active. 7. when v bat > v cc > v rst , v out remains connected to v cc until v cc drops below v rst . 8. when v rst > v cc > v bat , v out remains connected to v cc until v cc drops below the battery voltage (v bat ) ? 75mv. 9. for v cc falling. push-button reset input (stm703/704/819) t mlmh t mr mr pulse width stm703/704 150 ns stm819 1 s t mlrl t mrd mr to rst output delay stm703/704 250 ns stm819 120 ns mr glitch immunity stm819 100 ns mr pull-up resistor mr = 0v; v cc = 5v 45 63 85 k ? watchdog timer (not available on stm703/704/819) t wd watchdog timeout period v rst (max) < v cc < 5.5v 1.12 1.60 2.24 s wdi pulse width v rst (max) < v cc < 5.5v 50 ns chip-enable gating (stm818 only) e -to-e con resistance v cc = v rst (max) 40 150 ? e -to-e con propagation delay 4.5v < v cc < 5.5v 27ns reset-to-e con high delay (power-down) 15 s e con short circuit current v cc = 5v, disable mode, e = logic high, e con = 0v 0.10.752.0ma sym alter- native description test condition (1) min typ max unit
STM690A/692a/703/ 704/802/805/817/818/819 28/33 package mechanical figure 40. so8 ? 8-lead plastic small outline, 150 mils body width, package mech. drawing note: drawing is not to scale. table 8. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical data symb mm inches typ min max typ min max a ? 1.35 1.75 ? 0.053 0.069 a1 ? 0.10 0.25 ? 0.004 0.010 b ? 0.33 0.51 ? 0.013 0.020 c ? 0.19 0.25 ? 0.007 0.010 d ? 4.80 5.00 ? 0.189 0.197 ddd ? ?0.10? ?0.004 e ? 3.80 4.00 ? 0.150 0.157 e1.27? ?0.050? ? h ? 5.80 6.20 ? 0.228 0.244 h ? 0.25 0.50 ? 0.010 0.020 l ? 0.40 0.90 ? 0.016 0.035 ?08?08 n8 8 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
29/33 STM690A/692a/703/ 704/802/805/817/818/819 figure 41. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, outline note: drawing is not to scale. table 9. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, mechanical data symb mm inches typ min max typ min max a ? ?1.10? ?0.043 a1 ? 0.05 0.15 ? 0.002 0.006 a2 0.85 0.75 0.95 0.034 0.030 0.037 b ? 0.25 0.40 ? 0.010 0.016 c ? 0.13 0.23 ? 0.005 0.009 cp ? ? 0.10 ? ? 0.004 d 3.00 2.90 3.10 0.118 0.114 0.122 e0.65? ?0.026? ? e 4.90 4.65 5.15 0.193 0.183 0.203 e1 3.00 2.90 3.10 0.118 0.114 0.122 l 0.55 0.40 0.70 0.022 0.016 0.030 l1 0.95 ? ? 0.037 ? ? ?06?06 n8 8 tssop8bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
STM690A/692a/703/ 704/802/805/817/818/819 30/33 part numbering table 10. ordering information scheme note: 1. contact local st sales office for availability. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: STM690A m 6 e device type STM690A/692a/703/704/802/805/817/818/819 reset threshold voltage STM690A/703: blank = v rst = 4.50v to 4.75v stm8xxl: l = v rst = 4.50v to 4.75v stm692a/704: blank = v rst = 4.25v to 4.50v stm8xxm: m = v rst = 4.25v to 4.50v package m = so8 ds (1) = tssop8 temperature range 6 = ?40 to 85c shipping method e = tubes (pb-free - eco pack ? ) f = tape & reel (pb-free - eco pack ? )
31/33 STM690A/692a/703/ 704/802/805/817/818/819 table 11. marking description part number reset threshold package topside marking STM690A 4.65v so8 690a stm692a 4.65v so8 692a stm703 4.65v so8 703 stm704 4.40v so8 704 stm802l 4.65v so8 802l stm802m 4.40v so8 802m stm805l 4.65v so8 805l stm817l 4.65v so8 817l tssop8 stm817m 4.40v so8 817m tssop8 stm818l 4.65v so8 818l tssop8 stm818m 4.40v so8 818m tssop8 stm819l 4.65v so8 819l tssop8 stm819m 4.40v so8 819m tssop8
STM690A/692a/703/ 704/802/805/817/818/819 32/33 revision history table 12. document revision history date version revision details october 2003 1.0 first issue 31-oct-03 1.1 update dc characteristics (table 7 ) 22-dec-03 2.0 reformatted; updated characteristics (figure 1 , 3 , 4 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 17 ; table 3 , 4 , 7 , 9 , 11 ) 16-jan-04 2.1 add typical characteristics (figure 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 ) 08-apr-04 2.2 update characteristics (figure 13 , 21 , 26 , 28 , 29 , 30 , 33 , 34 ; table 1 , 7 ) 25-may-04 3.0 remove references to ?open drain? (figure 2 , 5 , 8 ; table 2 ); update characteristics (table 3 , 7 ) 05-jul-04 4.0 update package availability, pin description; promote document (figure 1 , 14 , 15 ; table 3 . 7 , 10 ) 29-sep-04 5.0 clarify root part numbers, pin descriptions (figure 11 , 13 , 36 ; table 7 , 10 )
33/33 STM690A/692a/703/ 704/802/805/817/818/819 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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